PB'16 competition: satisfaction and optimization track: results by benchmark

Results by benchmark for category optimisation, small integers, linear constraints (OPT-SMALLINT-LIN), subcategory Handmade, subsubcategory Synthesis PTL/CMOS Circuits

This page displays the results of the different solvers for each benchmark for category optimisation, small integers, linear constraints (OPT-SMALLINT-LIN), subcategory Handmade, subsubcategory Synthesis PTL/CMOS Circuits

REMINDER

Keep in mind that the 'Best result' columns only provide the best result given by one of the solvers. This 'Best result' may be wrong in case of an UNSATISFIABLE or OPTIMUM FOUND answer (because there's no efficient way to check these answers).

Description of a cell contents:

Cell exampleMeaning
AnswerSolver result
f=...value of the objective function for the model reported by the solver
TT=...Total Time (TT): this is the CPU time (in seconds) used by the solver until termination. This time is only meaningful for complete solvers because incomplete solvers will always run until they time out
Remember that CPU time and wall clock time are two very different notions. The CPU time represents the time during which the instructions of the solver were executed by the processor. The wall clock time represents how much time ellapsed on the clock. For a same event, the CPU time may be either smaller or greater than the wall clock time depending on the number of threads of execution and the number of processors.

Meaning of some abbreviations:

AbbreviationMeaning
f=...Value of the objective function
TOTime Out
MOMem. Out (out of memory)

Meaning of the different colors:

ColorMeaning
textthe solver cannot handle this instance
textthe solver gave no answer
textthe solver could give an answer (SAT)
textthe solver gave a definitive answer (OPTIMUM FOUND or UNSAT)
textthe solver performed better than the other ones on that instance (complete solvers point of view)
textthe solver performed better than the other ones on that instance (incomplete solvers point of view)
textthe solver was ended by a signal or other problem
textthe solver gave an incomplete answer
textthe solver gave a wrong answer

For better readability, you may choose to hide some solvers:
cdcl-cuttingplanes OPT binary search 2016-05-01 (complete)
cdcl-cuttingplanes OPT linear search 2016-05-01 (complete)
minisatp 2012-10-02 git-d91742b (complete)
NaPS 1.02 (complete)
Open-WBO PB16 (complete)
Open-WBO-LSU PB16 (complete)
Sat4j PB 2.3.6 Res+CP PB16 (complete)
Sat4j PB 2.3.6 Resolution PB16 (complete)
toysat 2016-05-02 (complete)

Bench nameBest results
on this
instance
cdcl-cuttingplanes OPT binary search
2016-05-01
(complete)
cdcl-cuttingplanes OPT linear search
2016-05-01
(complete)
minisatp
2012-10-02 git-d91742b
(complete)
NaPS
1.02
(complete)
Open-WBO
PB16
(complete)
Open-WBO-LSU
PB16
(complete)
Sat4j PB 2.3.6 Res+CP
PB16
(complete)
Sat4j PB 2.3.6 Resolution
PB16
(complete)
toysat
2016-05-02
(complete)
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-9symml.opb
SAT
f=4693
TT=1800.01
T1=1800.3
? (TO)

TT=1800.01

? (TO)

TT=1800.02

SAT (TO)
f=4899
TT=1800.03
T1=1800.4
SAT (TO)
f=6227
TT=1800.01
T1=1800.3
SAT (TO)
f=4693
TT=1800.01
T1=1800.3
SAT (TO)
f=5202
TT=1800.19
T1=1800.4
SAT (TO)
f=5498
TT=1800.69
T1=37.87
SAT (TO)
f=5962
TT=1800.56
T1=1.56
? (TO)

TT=1800.08

normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-b1.opb
OPT
f=128
TT=0.001
T1=0
OPT
f=128
TT=0.023
T1=0.02
OPT
f=128
TT=0.013
T1=0.01
OPT
f=128
TT=0.003
T1=0
OPT
f=128
TT=0.029
T1=0.02
OPT
f=128
TT=0.002
T1=0
OPT
f=128
TT=0.001
T1=0
OPT
f=128
TT=0.183
T1=1.8
OPT
f=128
TT=0.174
T1=0.14
OPT
f=128
TT=0.022
T1=0.02
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-C17.opb
OPT
f=260
TT=0
T1=0
OPT
f=260
TT=0.022
T1=0.02
OPT
f=260
TT=0.015
T1=0.01
OPT
f=260
TT=0.001
T1=0
OPT
f=260
TT=0.008
T1=0.01
OPT
f=260
TT=0
T1=0
OPT
f=260
TT=0.001
T1=0
OPT
f=260
TT=0.174
T1=1.13
OPT
f=260
TT=0.175
T1=0.14
OPT
f=260
TT=0.022
T1=0.01
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-C432.opb
SAT
f=4834
TT=1800.02
T1=1800.3
? (TO)

TT=1800.02

? (TO)

TT=1800.02

SAT (TO)
f=5635
TT=1800.03
T1=1800.4
SAT (TO)
f=7143
TT=1800.1
T1=1800.4
SAT (TO)
f=4834
TT=1800.02
T1=1800.3
SAT (TO)
f=5552
TT=1800.46
T1=1800.4
SAT (TO)
f=6156
TT=1800.14
T1=125.58
SAT (TO)
f=6879
TT=1800.02
T1=1181.17
? (TO)

TT=1800.06

normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-c8.opb
OPT
f=1194
TT=11.714
T1=11.71
? (TO)

TT=1800.02

? (TO)

TT=1800.02

SAT (TO)
f=1302
TT=1800.08
T1=1800.4
SAT (TO)
f=1737
TT=1800.02
T1=1800.3
OPT
f=1194
TT=11.714
T1=11.71
SAT (TO)
f=1221
TT=1800.07
T1=1800.4
SAT (TO)
f=1482
TT=1800.16
T1=296.34
SAT (TO)
f=1557
TT=1800.75
T1=1163.63
OPT
f=1194
TT=178.038
T1=80.91
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-cc.opb
OPT
f=1567
TT=0.005
T1=0
OPT
f=1567
TT=1.487
T1=1.48
OPT
f=1567
TT=3.514
T1=3.51
SAT (TO)
f=1588
TT=1800.02
T1=1800.3
SAT (TO)
f=1585
TT=1800.02
T1=1800.3
OPT
f=1567
TT=0.005
T1=0
SAT (TO)
f=1597
TT=1800.1
T1=1800.4
SAT (TO)
f=1603
TT=1800.04
T1=26.23
SAT (TO)
f=1653
TT=1800.69
T1=9.08
OPT
f=1567
TT=8.867
T1=3.27
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-cm42a.opb
OPT
f=694
TT=0.068
T1=0.06
OPT
f=694
TT=13.552
T1=13.55
OPT
f=694
TT=7.441
T1=7.44
OPT
f=694
TT=89.508
T1=89.52
OPT
f=694
TT=32.095
T1=32.09
OPT
f=694
TT=0.068
T1=0.06
OPT
f=694
TT=54.005
T1=54.01
SAT (TO)
f=694
TT=1800.93
T1=224.73
SAT (TO)
f=801
TT=1800.08
T1=1556.84
? (TO)

TT=1800.02

normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-cmb.opb
OPT
f=1053
TT=0.406
T1=0.4
? (TO)

TT=1800.02

? (TO)

TT=1800.02

SAT (TO)
f=1187
TT=1800.1
T1=1800.4
SAT (TO)
f=1524
TT=1800.02
T1=1800.3
OPT
f=1053
TT=0.406
T1=0.4
SAT (TO)
f=1101
TT=1800.1
T1=1800.4
SAT (TO)
f=1398
TT=1800.53
T1=110.32
SAT (TO)
f=1429
TT=1800.66
T1=1215.5
? (TO)

TT=1800.03

normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-mux.opb
OPT
f=872
TT=8.669
T1=8.67
? (TO)

TT=1800.02

? (TO)

TT=1800.02

SAT (TO)
f=1218
TT=1800.01
T1=1800.3
SAT (TO)
f=872
TT=1800.02
T1=1800.3
OPT
f=872
TT=8.669
T1=8.67
SAT (TO)
f=986
TT=1800.08
T1=1800.4
SAT (TO)
f=1232
TT=1800.26
T1=897.9
SAT (TO)
f=1473
TT=1800.67
T1=0.39
? (TO)

TT=1800.02

normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/synthesis-ptl-cmos-circuits/
normalized-my_adder.opb
OPT
f=4561
TT=0.065
T1=0.06
? (TO)

TT=1800.01

? (TO)

TT=1800.02

SAT (TO)
f=5209
TT=1800.02
T1=1800.4
SAT (TO)
f=6071
TT=1800.02
T1=1800.3
OPT
f=4561
TT=0.065
T1=0.06
SAT (TO)
f=5301
TT=1800.15
T1=1800.4
SAT (TO)
f=5246
TT=1800.09
T1=546.42
SAT (TO)
f=6092
TT=1800.05
T1=0.28
? (TO)

TT=1800.08




Statisticscdcl-cuttingplanes OPT binary search
2016-05-01
(complete)
cdcl-cuttingplanes OPT linear search
2016-05-01
(complete)
minisatp
2012-10-02 git-d91742b
(complete)
NaPS
1.02
(complete)
Open-WBO
PB16
(complete)
Open-WBO-LSU
PB16
(complete)
Sat4j PB 2.3.6 Res+CP
PB16
(complete)
Sat4j PB 2.3.6 Resolution
PB16
(complete)
toysat
2016-05-02
(complete)
Number of times the solver is able to give the best known answer4433103224
Number of times the solver is the best solver from a complete solver point of view
(i.e. best known answer and best TT time)
000091000