PB'10 competition: satisfaction and optimization track: results by benchmark

Results by benchmark for category optimisation, small integers, linear constraints (OPT-SMALLINT-LIN), subcategory Handmade, subsubcategory Synthesis PTL/CMOS Circuits

This page displays the results of the different solvers for each benchmark for category optimisation, small integers, linear constraints (OPT-SMALLINT-LIN), subcategory Handmade, subsubcategory Synthesis PTL/CMOS Circuits

REMINDER

Keep in mind that the 'Best result' columns only provide the best result given by one of the solvers. This 'Best result' may be wrong in case of an UNSATISFIABLE or OPTIMUM FOUND answer (because there's no efficient way to check these answers).

Description of a cell contents:

Cell exampleMeaning
AnswerSolver result
f=...value of the objective function for the model reported by the solver
TT=...Total Time (TT): this is the CPU time (in seconds) used by the solver until termination. This time is only meaningful for complete solvers because incomplete solvers will always run until they time out
Remember that CPU time and wall clock time are two very different notions. The CPU time represents the time during which the instructions of the solver were executed by the processor. The wall clock time represents how much time ellapsed on the clock. For a same event, the CPU time may be either smaller or greater than the wall clock time depending on the number of threads of execution and the number of processors.

Meaning of some abbreviations:

AbbreviationMeaning
f=...Value of the objective function
TOTime Out
MOMem. Out (out of memory)

Meaning of the different colors:

ColorMeaning
textthe solver cannot handle this instance
textthe solver gave no answer
textthe solver could give an answer (SAT)
textthe solver gave a definitive answer (OPTIMUM FOUND or UNSAT)
textthe solver performed better than the other ones on that instance (complete solvers point of view)
textthe solver performed better than the other ones on that instance (incomplete solvers point of view)
textthe solver was ended by a signal or other problem
textthe solver gave an incomplete answer
textthe solver gave a wrong answer

For better readability, you may choose to hide some solvers:
bsolo 3.2 Card (complete)
bsolo 3.2 Cl (complete)
pb_cplex 2010-06-29 (complete)
PB/CT 0.1 (complete)
PB/CT 0.1 fixed (complete)
PBPASSolver 2010-06-13 (complete)
SAT4J PB CuttingPlanes 2.2.0 2010-05-26 (complete)
SAT4J PB RES // CP 2.2.0 2010-05-31 (complete)
SAT4J PB Resolution 2.2.0 2010-05-26 (complete)
SCIPclp SCIP 1.2.1.2 with Clp 1.11.1 (Release Version) as LP solver (complete)
SCIPnone SCIP 1.2.1.2 without any LP solver (complete)
SCIPspx SCIP 1.2.1.2 with SoPlex 1.4.2 (CVS Version 30.5.2010) as LP solver (complete)
SCIPspx SCIP 1.2.1.3 with SoPlex 1.4.2 (CVS Version 30.5.2010) as LP solver (complete)
wbo 1.4b (complete)
wbo 1.4b (fixed) (complete)

Bench nameBest results
on this
instance		bsolo
3.2 Card
(complete)		bsolo
3.2 Cl
(complete)		pb_cplex
2010-06-29
(complete)		PB/CT
0.1
(complete)		PB/CT
0.1 fixed
(complete)		PBPASSolver
2010-06-13
(complete)		SAT4J PB CuttingPlanes
2.2.0 2010-05-26
(complete)		SAT4J PB RES // CP
2.2.0 2010-05-31
(complete)		SAT4J PB Resolution
2.2.0 2010-05-26
(complete)		SCIPclp
SCIP 1.2.1.2 with Clp 1.11.1 (Release Version) as LP solver
(complete)		SCIPnone
SCIP 1.2.1.2 without any LP solver
(complete)		SCIPspx
SCIP 1.2.1.2 with SoPlex 1.4.2 (CVS Version 30.5.2010) as LP solver
(complete)		SCIPspx
SCIP 1.2.1.3 with SoPlex 1.4.2 (CVS Version 30.5.2010) as LP solver
(complete)		wbo
1.4b
(complete)		wbo
1.4b (fixed)
(complete)
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-9symml.opb 		OPT
f=4517
TT=0.387
T1=0.38
 SAT
f=4782
TT=1798.2
T1=1737.86
 SAT
f=4787
TT=1798.01
T1=1798.03
 OPT
f=4517
TT=0.387
T1=0.38
 SAT (TO)
f=5035
TT=1800.04
T1=1500.5
 SAT (TO)
f=5100
TT=1800.02
T1=699.6
 ? (TO)

TT=1800.07

 SAT (TO)
f=5576
TT=1800.21
T1=574.04
 ? (TO)

TT=1803.83

 SAT (TO)
f=5301
TT=1800.19
T1=973.37
 OPT
f=4517
TT=0.906
T1=0.89
 SAT (MO)
f=5255
TT=1760.68
T1=1549.66
 OPT
f=4517
TT=4.742
T1=3.51
 OPT
f=4517
TT=3.182
T1=3.16
 ? (TO)

TT=1800.19

 ? (TO)

TT=1800.02
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-C432.opb 		OPT
f=4822
TT=0.534
T1=0.53
 SAT
f=5435
TT=1798.02
T1=713.64
 SAT
f=5809
TT=1798.02
T1=1513.68
 OPT
f=4822
TT=0.534
T1=0.53
 SAT (TO)
f=5584
TT=1800.06
T1=0.13
 SAT (TO)
f=5584
TT=1800.07
T1=0.13
 ? (TO)

TT=1800.07

 SAT (TO)
f=5811
TT=1800.23
T1=1330.84
 SAT (TO)
f=5936
TT=1800.63
T1=778.92
 SAT (TO)
f=6005
TT=1800.18
T1=1785.64
 OPT
f=4822
TT=1.205
T1=1.18
 SAT (TO)
f=5918
TT=1800.25
T1=495.01
 OPT
f=4822
TT=4.556
T1=4.53
 OPT
f=4822
TT=6.18
T1=6.16
 ? (TO)

TT=1800.16

 ? (TO)

TT=1800.05
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-c8.opb 		OPT
f=1194
TT=0.07
T1=0.06
 OPT
f=1194
TT=0.807
T1=0.76
 OPT
f=1194
TT=0.806
T1=0.76
 OPT
f=1194
TT=0.07
T1=0.06
 SAT (TO)
f=1249
TT=1800.07
T1=756.2
 SAT (TO)
f=1252
TT=1800.09
T1=1343.29
 ? (TO)

TT=1800.07

 SAT (TO)
f=1495
TT=1800.33
T1=390.77
 ? (TO)

TT=1803.47

 SAT (TO)
f=1353
TT=1800.2
T1=887
 OPT
f=1194
TT=0.191
T1=0.18
 SAT (TO)
f=1283
TT=1802.23
T1=452.13
 OPT
f=1194
TT=0.201
T1=0.19
 OPT
f=1194
TT=0.215
T1=0.2
 OPT
f=1194
TT=184.79
T1=184.81
 OPT
f=1194
TT=185.059
T1=185.06
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-cc.opb 		OPT
f=1567
TT=0.032
T1=0.03
 OPT
f=1567
TT=0.405
T1=0.38
 OPT
f=1567
TT=0.388
T1=0.37
 OPT
f=1567
TT=0.032
T1=0.03
 SAT (TO)
f=1569
TT=1800.11
T1=924.67
 SAT (TO)
f=1576
TT=1800.04
T1=1775.01
 ? (TO)

TT=1800.01

 SAT (TO)
f=1585
TT=1800.25
T1=1017.1
 SAT (TO)
f=1585
TT=1802.89
T1=418.91
 SAT (TO)
f=1620
TT=1800.16
T1=1529.14
 OPT
f=1567
TT=0.061
T1=0.04
 SAT (TO)
f=1763
TT=1800.04
T1=1317.21
 OPT
f=1567
TT=0.062
T1=0.05
 OPT
f=1567
TT=0.112
T1=0.04
 ? (TO)

TT=1800.14

 ? (TO)

TT=1800.21
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-cm42a.opb 		OPT
f=694
TT=0.021
T1=0
 OPT
f=694
TT=0.021
T1=0
 OPT
f=694
TT=0.021
T1=0
 OPT
f=694
TT=0.04
T1=0.03
 SAT (TO)
f=694
TT=1800.11
T1=488.38
 SAT (TO)
f=694
TT=1800.11
T1=868.5
 ? (TO)

TT=1800.02

 SAT (TO)
f=795
TT=1800.69
T1=115.59
 ? (TO)

TT=1803.96

 SAT (TO)
f=694
TT=1800.23
T1=158.1
 OPT
f=694
TT=0.055
T1=0.04
 SAT (TO)
f=694
TT=1800.09
T1=2.55
 OPT
f=694
TT=0.055
T1=0.04
 OPT
f=694
TT=0.127
T1=0.11
 ? (TO)

TT=1800.2

 ? (TO)

TT=1800.12
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-cmb.opb 		OPT
f=1053
TT=0.096
T1=0.09
 OPT
f=1053
TT=0.793
T1=0.72
 OPT
f=1053
TT=0.789
T1=0.71
 OPT
f=1053
TT=0.096
T1=0.09
 SAT (TO)
f=1127
TT=1800.11
T1=1601.79
 SAT (TO)
f=1123
TT=1800.02
T1=1125.88
 ? (TO)

TT=1800.05

 SAT (TO)
f=1373
TT=1800.15
T1=28.63
 ? (TO)

TT=1803.87

 SAT (TO)
f=1191
TT=1800.24
T1=1724.02
 OPT
f=1053
TT=0.17
T1=0.15
 SAT (TO)
f=1192
TT=1800.04
T1=677.78
 OPT
f=1053
TT=0.138
T1=0.12
 OPT
f=1053
TT=0.174
T1=0.16
 OPT
f=1053
TT=184.57
T1=184.59
 OPT
f=1053
TT=184.725
T1=184.73
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-mux.opb 		OPT
f=872
TT=0.024
T1=0.02
 OPT
f=872
TT=0.024
T1=0.02
 OPT
f=872
TT=0.025
T1=0.02
 OPT
f=872
TT=0.047
T1=0.04
 SAT (TO)
f=1037
TT=1800.05
T1=1775.54
 SAT (TO)
f=1017
TT=1800.08
T1=1617.13
 ? (TO)

TT=1800.1

 SAT (TO)
f=1086
TT=1800.14
T1=21.1
 ? (TO)

TT=1803.79

 SAT (TO)
f=1141
TT=1800.2
T1=3.09
 OPT
f=872
TT=0.088
T1=0.07
 SAT (TO)
f=872
TT=1800.06
T1=1.41
 OPT
f=872
TT=0.09
T1=0.08
 OPT
f=872
TT=0.081
T1=0.07
 OPT
f=872
TT=184.666
T1=184.71
 OPT
f=872
TT=184.909
T1=184.92
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/synthesis-ptl-cmos-circuits/
normalized-my_adder.opb 		OPT
f=4561
TT=0.371
T1=0.36
 OPT
f=4561
TT=28.643
T1=2.68
 OPT
f=4561
TT=28.027
T1=2.65
 OPT
f=4561
TT=0.371
T1=0.36
 SAT (TO)
f=5272
TT=1800.02
T1=819.63
 SAT (TO)
f=5256
TT=1800.07
T1=1134.5
 ? (TO)

TT=1800.04

 SAT (TO)
f=5089
TT=1800.28
T1=131.14
 ? (TO)

TT=1803.4

 SAT (TO)
f=5528
TT=1800.13
T1=1399.27
 OPT
f=4561
TT=1.293
T1=0.84
 SAT (TO)
f=5919
TT=1800.09
T1=1091.94
 OPT
f=4561
TT=1.251
T1=0.89
 OPT
f=4561
TT=1.961
T1=1.9
 ? (TO)

TT=1800.06

 ? (TO)

TT=1800.17



Statisticsbsolo
3.2 Card
(complete)		bsolo
3.2 Cl
(complete)		pb_cplex
2010-06-29
(complete)		PB/CT
0.1
(complete)		PB/CT
0.1 fixed
(complete)		PBPASSolver
2010-06-13
(complete)		SAT4J PB CuttingPlanes
2.2.0 2010-05-26
(complete)		SAT4J PB RES // CP
2.2.0 2010-05-31
(complete)		SAT4J PB Resolution
2.2.0 2010-05-26
(complete)		SCIPclp
SCIP 1.2.1.2 with Clp 1.11.1 (Release Version) as LP solver
(complete)		SCIPnone
SCIP 1.2.1.2 without any LP solver
(complete)		SCIPspx
SCIP 1.2.1.2 with SoPlex 1.4.2 (CVS Version 30.5.2010) as LP solver
(complete)		SCIPspx
SCIP 1.2.1.3 with SoPlex 1.4.2 (CVS Version 30.5.2010) as LP solver
(complete)		wbo
1.4b
(complete)		wbo
1.4b (fixed)
(complete)
Number of times the solver is able to give the best known answer668000000808800
Number of times the solver is the best solver from a complete solver point of view
(i.e. best known answer and best TT time)		216000000000000