PB'09 competition: results by benchmark

Results by benchmark for category optimisation, small integers, linear constraints (OPT-SMALLINT-LIN), subcategory Handmade, subsubcategory Synthesis PTL/CMOS Circuits

This page displays the results of the different solvers for each benchmark for category optimisation, small integers, linear constraints (OPT-SMALLINT-LIN), subcategory Handmade, subsubcategory Synthesis PTL/CMOS Circuits

REMINDER

Keep in mind that the 'Best result' columns only provide the best result given by one of the solvers. This 'Best result' may be wrong in case of an UNSATISFIABLE or OPTIMUM FOUND answer (because there's no efficient way to check these answers).

Description of a cell contents:

Cell exampleMeaning
AnswerSolver result
f=...value of the objective function for the model reported by the solver
TT=...Total Time (TT): this is the CPU time (in seconds) used by the solver until termination. This time is only meaningful for complete solvers because incomplete solvers will always run until they time out
Remember that CPU time and wall clock time are two very different notions. The CPU time represents the time during which the instructions of the solver were executed by the processor. The wall clock time represents how much time ellapsed on the clock. For a same event, the CPU time may be either smaller or greater than the wall clock time depending on the number of threads of execution and the number of processors.

Meaning of some abbreviations:

AbbreviationMeaning
f=...Value of the objective function
TOTime Out
MOMem. Out (out of memory)

Meaning of the different colors:

ColorMeaning
textthe solver cannot handle this instance
textthe solver gave no answer
textthe solver could give an answer (SAT)
textthe solver gave a definitive answer (OPTIMUM FOUND or UNSAT)
textthe solver performed better than the other ones on that instance (complete solvers point of view)
textthe solver performed better than the other ones on that instance (incomplete solvers point of view)
textthe solver was ended by a signal or other problem
textthe solver gave an incomplete answer
textthe solver gave a wrong answer

For better readability, you may choose to hide some solvers:
bsolo 3.1 (complete)
bsolo 3.1 cl (complete)
bsolo 3.1 pb (complete)
pbclasp 2009-04-24 (complete)
SAT4J Pseudo CP 2.1.1 (complete)
SAT4J Pseudo Resolution 2.1.1 (complete)
SCIPclp SCIP 1.1.0.7 with CLP 1.8.2 (complete)
SCIPspx SCIP 1.1.0.7 with SoPLEX 1.4.1(24.4.2009) (complete)
wbo 1.0 (complete)

Bench nameBest results
on this
instance		bsolo
3.1
(complete)		bsolo
3.1 cl
(complete)		bsolo
3.1 pb
(complete)		pbclasp
2009-04-24
(complete)		SAT4J Pseudo CP
2.1.1
(complete)		SAT4J Pseudo Resolution
2.1.1
(complete)		SCIPclp
SCIP 1.1.0.7 with CLP 1.8.2
(complete)		SCIPspx
SCIP 1.1.0.7 with SoPLEX 1.4.1(24.4.2009)
(complete)		wbo
1.0
(complete)
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-9symml.opb 		OPT
f=4517
TT=4.697
T1=3.51
 SAT
f=4782
TT=1798.02
T1=1734.37
 SAT
f=4791
TT=1798.01
T1=1798.1
 SAT
f=4647
TT=1798.15
T1=1585.93
 SAT (TO)
f=4985
TT=1800.11
T1=0.03
 SAT (TO)
f=5840
TT=1800.42
T1=29.1
 SAT (TO)
f=5987
TT=1801.49
T1=1.16
 OPT
f=4517
TT=3.687
T1=2.7
 OPT
f=4517
TT=4.697
T1=3.51
 ? (TO)

TT=1800.18
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-C432.opb 		OPT
f=4822
TT=4.343
T1=4.32
 SAT
f=5435
TT=1798.04
T1=664.84
 SAT
f=5809
TT=1798.02
T1=1530.79
 SAT
f=5809
TT=1798.02
T1=1732.13
 SAT (TO)
f=5713
TT=1800.07
T1=0.04
 SAT (TO)
f=6879
TT=1800.38
T1=135.92
 SAT (TO)
f=6956
TT=1800.83
T1=0.96
 OPT
f=4822
TT=2.485
T1=2.47
 OPT
f=4822
TT=4.343
T1=4.32
 ? (TO)

TT=1800.16
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-c8.opb 		OPT
f=1194
TT=0.221
T1=0.21
 OPT
f=1194
TT=0.829
T1=0.78
 OPT
f=1194
TT=0.827
T1=0.78
 OPT
f=1194
TT=0.828
T1=0.78
 SAT (TO)
f=1414
TT=1800.13
T1=1355.07
 SAT (TO)
f=1476
TT=1800.52
T1=90.39
 SAT (TO)
f=1560
TT=1801.66
T1=655.56
 OPT
f=1194
TT=0.204
T1=0.19
 OPT
f=1194
TT=0.221
T1=0.21
 OPT
f=1194
TT=33.062
T1=33.06
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-cc.opb 		OPT
f=1567
TT=0.051
T1=0.04
 OPT
f=1567
TT=0.398
T1=0.38
 OPT
f=1567
TT=0.389
T1=0.37
 OPT
f=1567
TT=0.398
T1=0.38
 SAT (TO)
f=1625
TT=1800.04
T1=1585.75
 SAT (TO)
f=1576
TT=1801.22
T1=750.33
 SAT (TO)
f=1636
TT=1803.08
T1=742.43
 OPT
f=1567
TT=0.074
T1=0.06
 OPT
f=1567
TT=0.051
T1=0.04
 ? (TO)

TT=1800.17
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-cm42a.opb 		OPT
f=694
TT=0.02
T1=0
 OPT
f=694
TT=0.018
T1=0
 OPT
f=694
TT=0.02
T1=0
 OPT
f=694
TT=0.02
T1=0
 OPT
f=694
TT=1129.83
T1=308.62
 SAT (TO)
f=789
TT=1800.15
T1=296.57
 SAT (TO)
f=730
TT=1800.74
T1=1443.94
 OPT
f=694
TT=0.057
T1=0.04
 OPT
f=694
TT=0.057
T1=0.04
 ? (TO)

TT=1800.2
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-cmb.opb 		OPT
f=1053
TT=0.135
T1=0.13
 OPT
f=1053
TT=0.804
T1=0.73
 OPT
f=1053
TT=0.801
T1=0.72
 OPT
f=1053
TT=0.802
T1=0.72
 SAT (TO)
f=1163
TT=1800.11
T1=1609.19
 SAT (TO)
f=1303
TT=1800.14
T1=3.82
 SAT (TO)
f=1547
TT=1801.8
T1=102.54
 OPT
f=1053
TT=0.177
T1=0.16
 OPT
f=1053
TT=0.145
T1=0.13
 OPT
f=1053
TT=0.135
T1=0.13
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-mux.opb 		OPT
f=872
TT=0.024
T1=0.02
 OPT
f=872
TT=0.024
T1=0.02
 OPT
f=872
TT=0.024
T1=0.02
 OPT
f=872
TT=0.024
T1=0.02
 SAT (TO)
f=1101
TT=1800.07
T1=1202.04
 SAT (TO)
f=1294
TT=1800.57
T1=11.82
 SAT (TO)
f=1600
TT=1801.68
T1=1.21
 OPT
f=872
TT=0.089
T1=0.07
 OPT
f=872
TT=0.09
T1=0.08
 OPT
f=872
TT=0.066
T1=0.06
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/synthesis-ptl-cmos-circuits/
normalized-my_adder.opb 		OPT
f=4561
TT=1.193
T1=0.83
 OPT
f=4561
TT=28.778
T1=2.73
 OPT
f=4561
TT=28.62
T1=2.71
 OPT
f=4561
TT=28.795
T1=2.74
 SAT (TO)
f=5118
TT=1800.03
T1=0.02
 SAT (TO)
f=5441
TT=1800.37
T1=638.85
 SAT (TO)
f=6092
TT=1800.92
T1=0.62
 OPT
f=4561
TT=1.339
T1=0.91
 OPT
f=4561
TT=1.193
T1=0.83
 ? (TO)

TT=1800.21



Statisticsbsolo
3.1
(complete)		bsolo
3.1 cl
(complete)		bsolo
3.1 pb
(complete)		pbclasp
2009-04-24
(complete)		SAT4J Pseudo CP
2.1.1
(complete)		SAT4J Pseudo Resolution
2.1.1
(complete)		SCIPclp
SCIP 1.1.0.7 with CLP 1.8.2
(complete)		SCIPspx
SCIP 1.1.0.7 with SoPLEX 1.4.1(24.4.2009)
(complete)		wbo
1.0
(complete)
Number of times the solver is able to give the best known answer066100083
Number of times the solver is the best solver from a complete solver point of view
(i.e. best known answer and best TT time)		012000051