PB'09 competition: results by benchmark

Results by benchmark for category no optimisation, small integers, linear constraints (DEC-SMALLINT-LIN), subcategory Industrial, subsubcategory FPGA ...

This page displays the results of the different solvers for each benchmark for category no optimisation, small integers, linear constraints (DEC-SMALLINT-LIN), subcategory Industrial, subsubcategory FPGA ...

REMINDER

Keep in mind that the 'Best result' columns only provide the best result given by one of the solvers. This 'Best result' may be wrong in case of an UNSATISFIABLE or OPTIMUM FOUND answer (because there's no efficient way to check these answers).

Description of a cell contents:

Cell example	Meaning
Answer	Solver result
f=...	value of the objective function for the model reported by the solver
TT=...	Total Time (TT): this is the CPU time (in seconds) used by the solver until termination. This time is only meaningful for complete solvers because incomplete solvers will always run until they time out

Remember that CPU time and wall clock time are two very different notions. The CPU time represents the time during which the instructions of the solver were executed by the processor. The wall clock time represents how much time ellapsed on the clock. For a same event, the CPU time may be either smaller or greater than the wall clock time depending on the number of threads of execution and the number of processors.

Meaning of some abbreviations:

Abbreviation	Meaning
f=...	Value of the objective function
TO	Time Out
MO	Mem. Out (out of memory)

Meaning of the different colors:

Color	Meaning
text	the solver cannot handle this instance
text	the solver gave no answer
text	the solver could give an answer (SAT)
text	the solver gave a definitive answer (OPTIMUM FOUND or UNSAT)
text	the solver performed better than the other ones on that instance (complete solvers point of view)
text	the solver performed better than the other ones on that instance (incomplete solvers point of view)
text	the solver was ended by a signal or other problem
text	the solver gave an incomplete answer
text	the solver gave a wrong answer

For better readability, you may choose to hide some solvers:
BoolVar 2009-04-26 (complete)
bsolo 3.1 (complete)
bsolo 3.1 cl (complete)
bsolo 3.1 pb (complete)
pbclasp 2009-04-24 (complete)
SAT4J Pseudo CP 2.1.1 (complete)
SAT4J Pseudo Resolution 2.1.1 (complete)
SCIPclp SCIP 1.1.0.7 with CLP 1.8.2 (complete)
SCIPspx SCIP 1.1.0.7 with SoPLEX 1.4.1(24.4.2009) (complete)
wbo 1.0 (complete)

Bench name	Best results on this instance	BoolVar 2009-04-26 (complete)	bsolo 3.1 (complete)	bsolo 3.1 cl (complete)	bsolo 3.1 pb (complete)	pbclasp 2009-04-24 (complete)	SAT4J Pseudo CP 2.1.1 (complete)	SAT4J Pseudo Resolution 2.1.1 (complete)	SCIPclp SCIP 1.1.0.7 with CLP 1.8.2 (complete)	SCIPspx SCIP 1.1.0.7 with SoPLEX 1.4.1(24.4.2009) (complete)	wbo 1.0 (complete)
normalized-PB06/SATUNSAT-SMALLINT/submitted-PB05/ aloul/FPGA_SAT05/normalized-chnl10_11_pb.cnf.cr.opb	UNSAT TT=0.007	UNSAT TT=22.247	UNSAT TT=0.007	UNSAT TT=147.349	UNSAT TT=3.972	UNSAT TT=119.432	UNSAT TT=0.361	UNSAT TT=231.335	UNSAT TT=0.032	UNSAT TT=0.034	UNSAT TT=337.337
normalized-PB06/SATUNSAT-SMALLINT/submitted-PB05/ aloul/FPGA_SAT05/normalized-chnl10_15_pb.cnf.cr.opb	UNSAT TT=0.008	UNSAT TT=318.64	UNSAT TT=0.009	UNSAT TT=422.903	UNSAT TT=0.008	UNSAT TT=127.133	UNSAT TT=0.361	? (TO) TT=1800.41	UNSAT TT=0.034	UNSAT TT=0.038	? (TO) TT=1800.2
normalized-PB06/SATUNSAT-SMALLINT/submitted-PB05/ aloul/FPGA_SAT05/normalized-chnl10_20_pb.cnf.cr.opb	UNSAT TT=0.01	UNSAT TT=289.527	UNSAT TT=0.01	? TT=1798	UNSAT TT=0.011	UNSAT TT=139.5	UNSAT TT=0.405	? (TO) TT=1800.44	UNSAT TT=0.037	UNSAT TT=0.042	? (TO) TT=1800.18
normalized-PB06/SATUNSAT-SMALLINT/submitted-PB05/ aloul/FPGA_SAT05/normalized-chnl15_16_pb.cnf.cr.opb	UNSAT TT=0.017	? (TO) TT=1800.13	UNSAT TT=0.017	? TT=1798.01	UNSAT TT=0.068	? (TO) TT=1800.03	UNSAT TT=0.518	? (TO) TT=1800.42	UNSAT TT=0.04	UNSAT TT=0.043	? (TO) TT=1800.2
normalized-PB06/SATUNSAT-SMALLINT/submitted-PB05/ aloul/FPGA_SAT05/normalized-chnl15_20_pb.cnf.cr.opb	UNSAT TT=0.023	? (TO) TT=1800.07	UNSAT TT=0.023	? TT=1798.01	UNSAT TT=0.066	? (TO) TT=1800.04	UNSAT TT=0.462	? (TO) TT=1800.34	UNSAT TT=0.045	UNSAT TT=0.048	? (TO) TT=1800.2
normalized-PB06/SATUNSAT-SMALLINT/submitted-PB05/ aloul/FPGA_SAT05/normalized-chnl15_25_pb.cnf.cr.opb	UNSAT TT=0.026	? (TO) TT=1800.05	UNSAT TT=0.026	? TT=1798.03	UNSAT TT=0.071	? (TO) TT=1800.11	UNSAT TT=0.516	? (TO) TT=1800.37	UNSAT TT=0.047	UNSAT TT=0.059	? (TO) TT=1800.26
normalized-PB06/SATUNSAT-SMALLINT/submitted-PB05/ aloul/FPGA_SAT05/normalized-chnl20_21_pb.cnf.cr.opb	UNSAT TT=0.041	? (TO) TT=1800.13	UNSAT TT=0.042	? TT=1798.04	UNSAT TT=0.041	? (TO) TT=1800.1	UNSAT TT=0.687	? (TO) TT=1800.4	UNSAT TT=0.053	UNSAT TT=0.061	? (TO) TT=1800.18
normalized-PB06/SATUNSAT-SMALLINT/submitted-PB05/ aloul/FPGA_SAT05/normalized-chnl20_25_pb.cnf.cr.opb	UNSAT TT=0.039	? (TO) TT=1800.1	UNSAT TT=0.039	? TT=1798.04	UNSAT TT=0.238	? (TO) TT=1800.09	UNSAT TT=0.558	? (TO) TT=1800.37	UNSAT TT=0.055	UNSAT TT=0.069	? (TO) TT=1800.16
normalized-PB06/SATUNSAT-SMALLINT/submitted-PB05/ aloul/FPGA_SAT05/normalized-chnl20_30_pb.cnf.cr.opb	UNSAT TT=0.052	? (TO) TT=1800.07	UNSAT TT=0.052	? TT=1798.05	UNSAT TT=0.411	? (TO) TT=1800.08	UNSAT TT=0.665	? (TO) TT=1800.36	UNSAT TT=0.063	UNSAT TT=0.079	? (TO) TT=1800.17
normalized-PB06/SATUNSAT-SMALLINT/submitted-PB05/ aloul/FPGA_SAT05/normalized-chnl30_31_pb.cnf.cr.opb	UNSAT TT=0.092	? (TO) TT=1800.13	UNSAT TT=0.114	? TT=1798.14	UNSAT TT=0.097	? (TO) TT=1800.11	UNSAT TT=1.299	? (TO) TT=1800.4	UNSAT TT=0.092	UNSAT TT=0.113	? (TO) TT=1800.19
Bench name	Best results	BoolVar 2009-04-26 (complete)	bsolo 3.1 (complete)	bsolo 3.1 cl (complete)	bsolo 3.1 pb (complete)	pbclasp 2009-04-24 (complete)	SAT4J Pseudo CP 2.1.1 (complete)	SAT4J Pseudo Resolution 2.1.1 (complete)	SCIPclp SCIP 1.1.0.7 with CLP 1.8.2 (complete)	SCIPspx SCIP 1.1.0.7 with SoPLEX 1.4.1(24.4.2009) (complete)	wbo 1.0 (complete)
normalized-PB06/SATUNSAT-SMALLINT/submitted-PB05/ aloul/FPGA_SAT05/normalized-chnl30_35_pb.cnf.cr.opb	UNSAT TT=0.1	? (TO) TT=1800.15	UNSAT TT=0.125	? TT=1798.16	UNSAT TT=0.126	? (TO) TT=1800.12	UNSAT TT=0.819	? (TO) TT=1800.42	UNSAT TT=0.1	UNSAT TT=0.133	? (TO) TT=1800.31
normalized-PB06/SATUNSAT-SMALLINT/submitted-PB05/ aloul/FPGA_SAT05/normalized-chnl30_40_pb.cnf.cr.opb	UNSAT TT=0.108	? (MO) TT=308.988	UNSAT TT=0.184	? TT=1798.13	UNSAT TT=0.214	? (TO) TT=1800.11	UNSAT TT=0.843	? (TO) TT=1800.42	UNSAT TT=0.108	UNSAT TT=0.139	? (TO) TT=1800.21
normalized-PB06/SATUNSAT-SMALLINT/submitted-PB05/ aloul/FPGA_SAT05/normalized-chnl35_36_pb.cnf.cr.opb	UNSAT TT=0.123	? (MO) TT=101.715	UNSAT TT=0.186	? TT=1798.41	UNSAT TT=0.166	? (TO) TT=1800.04	UNSAT TT=1.688	? (TO) TT=1800.44	UNSAT TT=0.123	UNSAT TT=0.149	? (TO) TT=1800.26
normalized-PB06/SATUNSAT-SMALLINT/submitted-PB05/ aloul/FPGA_SAT05/normalized-chnl35_40_pb.cnf.cr.opb	UNSAT TT=0.131	? (MO) TT=93.108	UNSAT TT=0.306	? TT=1798.37	UNSAT TT=0.396	? (TO) TT=1800.05	UNSAT TT=1.053	? (TO) TT=1800.44	UNSAT TT=0.131	UNSAT TT=0.157	? (TO) TT=1800.24
normalized-PB06/SATUNSAT-SMALLINT/submitted-PB05/ aloul/FPGA_SAT05/normalized-chnl35_45_pb.cnf.cr.opb	UNSAT TT=0.139	? (MO) TT=172.651	UNSAT TT=0.223	? TT=1798.19	UNSAT TT=1.031	? (TO) TT=1800.06	UNSAT TT=1.074	? (TO) TT=1800.41	UNSAT TT=0.139	UNSAT TT=0.171	? (TO) TT=1800.25
normalized-PB06/SATUNSAT-SMALLINT/submitted-PB05/ aloul/FPGA_SAT05/normalized-chnl40_41_pb.cnf.cr.opb	UNSAT TT=0.161	? (MO) TT=38.912	UNSAT TT=0.293	? TT=1798.32	UNSAT TT=0.887	? (TO) TT=1800.13	UNSAT TT=1.85	? (TO) TT=1800.45	UNSAT TT=0.161	UNSAT TT=0.183	? (TO) TT=1800.35
normalized-PB06/SATUNSAT-SMALLINT/submitted-PB05/ aloul/FPGA_SAT05/normalized-chnl40_45_pb.cnf.cr.opb	UNSAT TT=0.174	? (MO) TT=76.21	UNSAT TT=0.279	? TT=1798.26	UNSAT TT=1.839	? (TO) TT=1800.06	UNSAT TT=1.124	? (TO) TT=1800.38	UNSAT TT=0.174	UNSAT TT=0.211	? (TO) TT=1800.29
normalized-PB06/SATUNSAT-SMALLINT/submitted-PB05/ aloul/FPGA_SAT05/normalized-chnl40_50_pb.cnf.cr.opb	UNSAT TT=0.199	? (MO) TT=638.054	UNSAT TT=0.371	? TT=1798.32	UNSAT TT=1.566	? (TO) TT=1800.06	UNSAT TT=1.166	? (TO) TT=1800.6	UNSAT TT=0.199	UNSAT TT=0.229	? (TO) TT=1800.27
normalized-PB06/SATUNSAT-SMALLINT/submitted-PB05/ aloul/FPGA_SAT05/normalized-chnl50_51_pb.cnf.cr.opb	UNSAT TT=0.272	? (MO) TT=99.574	UNSAT TT=0.644	? (MO) TT=1170.09	UNSAT TT=12.873	? (TO) TT=1800.11	UNSAT TT=2.379	? (TO) TT=1800.41	UNSAT TT=0.272	UNSAT TT=0.301	? (TO) TT=1800.36
normalized-PB06/SATUNSAT-SMALLINT/submitted-PB05/ aloul/FPGA_SAT05/normalized-chnl50_55_pb.cnf.cr.opb	UNSAT TT=0.297	? (MO) TT=173.527	UNSAT TT=0.897	? (MO) TT=1290.24	? TT=1798.43	? (TO) TT=1800.08	UNSAT TT=1.697	? (TO) TT=1800.46	UNSAT TT=0.297	UNSAT TT=0.317	? (TO) TT=1800.33
Bench name	Best results	BoolVar 2009-04-26 (complete)	bsolo 3.1 (complete)	bsolo 3.1 cl (complete)	bsolo 3.1 pb (complete)	pbclasp 2009-04-24 (complete)	SAT4J Pseudo CP 2.1.1 (complete)	SAT4J Pseudo Resolution 2.1.1 (complete)	SCIPclp SCIP 1.1.0.7 with CLP 1.8.2 (complete)	SCIPspx SCIP 1.1.0.7 with SoPLEX 1.4.1(24.4.2009) (complete)	wbo 1.0 (complete)
normalized-PB06/SATUNSAT-SMALLINT/submitted-PB05/ aloul/FPGA_SAT05/normalized-chnl50_60_pb.cnf.cr.opb	UNSAT TT=0.299	? (MO) TT=82.658	UNSAT TT=5.138	? (MO) TT=1468.41	UNSAT TT=0.922	? (TO) TT=1800.05	UNSAT TT=2.973	? (TO) TT=1800.43	UNSAT TT=0.299	UNSAT TT=0.333	? (TO) TT=1800.3
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga10_10_sat_pb.cnf.cr.opb	SAT TT=0.005 T1=0	SAT TT=0.265 T1=0.19	SAT TT=0.006 T1=0	SAT TT=0.009 T1=0	SAT TT=0.007 T1=0	SAT TT=0.042 T1=0.03	SAT TT=0.596 T1=0.46	SAT TT=1.054 T1=0.73	SAT TT=0.056 T1=0.04	SAT TT=0.063 T1=0.05	SAT TT=0.005 T1=0
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga10_8_sat_pb.cnf.cr.opb	SAT TT=0.002 T1=0	SAT TT=0.225 T1=0.17	SAT TT=0.005 T1=0	SAT TT=0.005 T1=0	SAT TT=0.004 T1=0	SAT TT=0.024 T1=0.02	SAT TT=8.865 T1=6.54	SAT TT=5.602 T1=5.03	SAT TT=0.06 T1=0.05	SAT TT=0.059 T1=0.05	SAT TT=0.002 T1=0
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga10_9_sat_pb.cnf.cr.opb	SAT TT=0.01 T1=0.01	SAT TT=0.294 T1=0.49	SAT TT=0.023 T1=0.02	SAT TT=0.02 T1=0.02	SAT TT=0.022 T1=0.02	SAT TT=0.02 T1=0.01	SAT TT=2.408 T1=1.36	SAT TT=3.896 T1=3.37	SAT TT=0.062 T1=0.05	SAT TT=0.064 T1=0.05	SAT TT=0.01 T1=0.01
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga11_10_sat_pb.cnf.cr.opb	SAT TT=0.003 T1=0	SAT TT=0.259 T1=0.2	SAT TT=0.006 T1=0	SAT TT=0.005 T1=0	SAT TT=0.005 T1=0	SAT TT=0.035 T1=0.03	SAT TT=0.7 T1=0.5	SAT TT=18.034 T1=17.45	SAT TT=0.071 T1=0.06	SAT TT=0.073 T1=0.06	SAT TT=0.003 T1=0
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga11_11_sat_pb.cnf.cr.opb	SAT TT=0.002 T1=0	SAT TT=0.276 T1=0.21	SAT TT=0.006 T1=0	SAT TT=0.005 T1=0	SAT TT=0.006 T1=0	SAT TT=0.227 T1=0.22	SAT TT=2.222 T1=1.23	SAT TT=32.323 T1=31.78	SAT TT=0.064 T1=0.05	SAT TT=0.081 T1=0.07	SAT TT=0.002 T1=0
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga11_9_sat_pb.cnf.cr.opb	SAT TT=0.002 T1=0	SAT TT=0.259 T1=0.18	SAT TT=0.004 T1=0	SAT TT=0.006 T1=0	SAT TT=0.005 T1=0	SAT TT=0.074 T1=0.07	SAT TT=2.701 T1=1.53	SAT TT=193.242 T1=192.78	SAT TT=0.067 T1=0.05	SAT TT=0.075 T1=0.06	SAT TT=0.002 T1=0
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga12_10_sat_pb.cnf.cr.opb	SAT TT=0.002 T1=0	SAT TT=0.278 T1=0.2	SAT TT=0.005 T1=0	SAT TT=0.005 T1=0	SAT TT=0.005 T1=0	SAT TT=0.619 T1=0.61	SAT TT=19.418 T1=17.16	? (TO) TT=1801.47	SAT TT=0.076 T1=0.06	SAT TT=0.085 T1=0.07	SAT TT=0.002 T1=0
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga12_11_sat_pb.cnf.cr.opb	SAT TT=0.013 T1=0.01	SAT TT=0.293 T1=0.23	SAT TT=0.032 T1=0.03	SAT TT=0.042 T1=0.04	SAT TT=0.019 T1=0.01	SAT TT=0.06 T1=0.05	SAT TT=2.85 T1=1.72	? (TO) TT=1800.44	SAT TT=0.084 T1=0.07	SAT TT=0.106 T1=0.09	SAT TT=0.013 T1=0.01
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga12_12_sat_pb.cnf.cr.opb	SAT TT=0.003 T1=0	SAT TT=0.319 T1=0.24	SAT TT=0.007 T1=0	SAT TT=0.008 T1=0	SAT TT=0.006 T1=0	SAT TT=0.106 T1=0.1	SAT TT=2.695 T1=1.55	SAT TT=1012.96 T1=1012.63	SAT TT=0.078 T1=0.07	SAT TT=0.094 T1=0.08	SAT TT=0.003 T1=0
Bench name	Best results	BoolVar 2009-04-26 (complete)	bsolo 3.1 (complete)	bsolo 3.1 cl (complete)	bsolo 3.1 pb (complete)	pbclasp 2009-04-24 (complete)	SAT4J Pseudo CP 2.1.1 (complete)	SAT4J Pseudo Resolution 2.1.1 (complete)	SCIPclp SCIP 1.1.0.7 with CLP 1.8.2 (complete)	SCIPspx SCIP 1.1.0.7 with SoPLEX 1.4.1(24.4.2009) (complete)	wbo 1.0 (complete)
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga13_11_sat_pb.cnf.cr.opb	SAT TT=0.003 T1=0	SAT TT=0.301 T1=0.22	SAT TT=0.25 T1=0.25	SAT TT=0.478 T1=0.47	SAT TT=0.011 T1=0.01	SAT TT=0.043 T1=0.04	SAT TT=298.823 T1=294.3	? (TO) TT=1800.46	SAT TT=0.091 T1=0.08	SAT TT=0.111 T1=0.1	SAT TT=0.003 T1=0
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga13_12_sat_pb.cnf.cr.opb	SAT TT=0.008 T1=0	SAT TT=0.333 T1=0.24	SAT TT=0.009 T1=0	SAT TT=0.015 T1=0.01	SAT TT=0.008 T1=0	SAT TT=0.114 T1=0.11	SAT TT=0.946 T1=0.65	SAT TT=1512.85 T1=1511.78	SAT TT=0.097 T1=0.08	SAT TT=0.193 T1=0.18	SAT TT=0.011 T1=0.01
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga13_13_sat_pb.cnf.cr.opb	SAT TT=0.007 T1=0	? (TO) TT=1800.1	SAT TT=0.009 T1=0.01	SAT TT=0.014 T1=0.01	SAT TT=0.011 T1=0.01	SAT TT=0.785 T1=0.77	SAT TT=1.574 T1=0.91	? (TO) TT=1800.32	SAT TT=0.091 T1=0.08	SAT TT=0.128 T1=0.11	SAT TT=0.007 T1=0
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga14_12_sat_pb.cnf.cr.opb	SAT TT=0.113 T1=0.1	SAT TT=0.342 T1=0.25	SAT TT=0.269 T1=0.26	SAT TT=0.8 T1=0.79	SAT TT=0.652 T1=0.65	SAT TT=12.418 T1=12.41	? (TO) TT=1800.27	? (TO) TT=1800.33	SAT TT=0.113 T1=0.1	SAT TT=0.113 T1=0.1	SAT TT=0.161 T1=0.16
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga14_13_sat_pb.cnf.cr.opb	SAT TT=0.004 T1=0	? (TO) TT=1800.11	SAT TT=0.008 T1=0	SAT TT=0.01 T1=0	SAT TT=0.008 T1=0	SAT TT=5.281 T1=5.27	SAT TT=4.869 T1=3.23	? (TO) TT=1800.28	SAT TT=0.11 T1=0.1	SAT TT=0.132 T1=0.12	SAT TT=0.004 T1=0
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga14_14_sat_pb.cnf.cr.opb	SAT TT=0.008 T1=0	? (TO) TT=1800.06	SAT TT=0.012 T1=0.01	SAT TT=0.024 T1=0.02	SAT TT=0.012 T1=0.01	SAT TT=0.645 T1=0.64	SAT TT=1.429 T1=0.79	? (TO) TT=1800.35	SAT TT=0.106 T1=0.09	SAT TT=0.124 T1=0.11	SAT TT=0.008 T1=0
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga15_13_sat_pb.cnf.cr.opb	SAT TT=0.005 T1=0	SAT TT=0.422 T1=0.6	SAT TT=0.009 T1=0	SAT TT=0.009 T1=0	SAT TT=0.009 T1=0	SAT TT=1122.34 T1=1122.62	SAT TT=136.291 T1=133.2	? (TO) TT=1800.37	SAT TT=0.123 T1=0.11	SAT TT=0.157 T1=0.14	SAT TT=0.005 T1=0
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga15_14_sat_pb.cnf.cr.opb	SAT TT=0.005 T1=0	SAT TT=0.387 T1=0.3	SAT TT=0.011 T1=0.01	SAT TT=0.011 T1=0.01	SAT TT=0.011 T1=0.01	SAT TT=14.185 T1=14.18	SAT TT=1.53 T1=0.92	? (TO) TT=1800.42	SAT TT=0.131 T1=0.12	SAT TT=0.174 T1=0.16	SAT TT=0.005 T1=0
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga15_15_sat_pb.cnf.cr.opb	SAT TT=0.01 T1=0	? (TO) TT=1800.08	SAT TT=0.012 T1=0.01	SAT TT=0.019 T1=0.01	SAT TT=0.012 T1=0.01	SAT TT=4.371 T1=4.36	SAT TT=11.375 T1=9.44	? (TO) TT=1800.35	SAT TT=0.124 T1=0.11	SAT TT=0.174 T1=0.16	SAT TT=0.01 T1=0
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga20_18_sat_pb.cnf.cr.opb	SAT TT=0.02 T1=0.02	SAT TT=0.624 T1=0.53	SAT TT=0.029 T1=0.02	SAT TT=5.243 T1=5.24	SAT TT=0.106 T1=0.1	? (TO) TT=1800.04	? (TO) TT=1800.25	? (TO) TT=1801.08	SAT TT=0.287 T1=0.27	SAT TT=0.426 T1=0.41	SAT TT=0.02 T1=0.02
Bench name	Best results	BoolVar 2009-04-26 (complete)	bsolo 3.1 (complete)	bsolo 3.1 cl (complete)	bsolo 3.1 pb (complete)	pbclasp 2009-04-24 (complete)	SAT4J Pseudo CP 2.1.1 (complete)	SAT4J Pseudo Resolution 2.1.1 (complete)	SCIPclp SCIP 1.1.0.7 with CLP 1.8.2 (complete)	SCIPspx SCIP 1.1.0.7 with SoPLEX 1.4.1(24.4.2009) (complete)	wbo 1.0 (complete)
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga20_19_sat_pb.cnf.cr.opb	SAT TT=0.009 T1=0.01	SAT TT=84.916 T1=84.85	SAT TT=0.022 T1=0.02	SAT TT=0.022 T1=0.02	SAT TT=0.023 T1=0.02	? (TO) TT=1800.09	SAT TT=425.71 T1=421	? (TO) TT=1800.4	SAT TT=0.36 T1=0.34	SAT TT=0.446 T1=0.43	SAT TT=0.009 T1=0.01
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga20_20_sat_pb.cnf.cr.opb	SAT TT=0.01 T1=0	? (TO) TT=1800.07	SAT TT=0.026 T1=0.02	SAT TT=0.025 T1=0.02	SAT TT=0.026 T1=0.02	? (TO) TT=1800.08	SAT TT=58.333 T1=54.64	? (TO) TT=1800.39	SAT TT=0.787 T1=0.77	SAT TT=0.433 T1=0.42	SAT TT=0.01 T1=0
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga25_23_sat_pb.cnf.cr.opb	SAT TT=0.048 T1=0.04	SAT TT=1.234 T1=1.13	SAT TT=11.532 T1=11.52	SAT TT=155.8 T1=155.83	SAT TT=0.048 T1=0.04	? (TO) TT=1800.05	? (TO) TT=1800.17	? (TO) TT=1800.32	SAT TT=50.913 T1=50.91	SAT TT=31.335 T1=31.35	SAT TT=0.208 T1=0.2
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga25_24_sat_pb.cnf.cr.opb	SAT TT=0.091 T1=0.08	SAT TT=1.318 T1=1.22	SAT TT=0.702 T1=0.7	SAT TT=0.091 T1=0.08	SAT TT=0.22 T1=0.21	? (TO) TT=1800.05	? (TO) TT=1800.22	? (TO) TT=1800.33	SAT TT=2.957 T1=2.94	SAT TT=32.725 T1=32.71	SAT TT=0.162 T1=0.16
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga25_25_sat_pb.cnf.cr.opb	SAT TT=0.037 T1=0.03	? (TO) TT=1800.09	SAT TT=0.056 T1=0.05	SAT TT=0.102 T1=0.1	SAT TT=0.239 T1=0.23	? (TO) TT=1800.04	SAT TT=601.689 T1=595.02	? (TO) TT=1800.4	SAT TT=25.745 T1=25.73	SAT TT=33.54 T1=33.53	SAT TT=0.037 T1=0.03
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga30_28_sat_pb.cnf.cr.opb	SAT TT=0.023 T1=0.02	SAT TT=2.152 T1=2.05	SAT TT=0.076 T1=0.07	SAT TT=0.075 T1=0.07	SAT TT=0.076 T1=0.07	? (TO) TT=1800.03	? (TO) TT=1800.35	? (TO) TT=1800.41	SAT TT=54.5 T1=54.5	SAT TT=57.339 T1=57.34	SAT TT=0.023 T1=0.02
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga30_29_sat_pb.cnf.cr.opb	SAT TT=0.139 T1=0.13	SAT TT=28.795 T1=28.7	SAT TT=0.258 T1=0.25	SAT TT=0.139 T1=0.13	SAT TT=0.584 T1=0.58	? (TO) TT=1800.12	? (TO) TT=1800.25	? (TO) TT=1800.37	SAT TT=42.653 T1=42.64	SAT TT=61.202 T1=61.2	SAT TT=0.532 T1=0.53
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga30_30_sat_pb.cnf.cr.opb	SAT TT=0.025 T1=0.02	? (TO) TT=1800.09	SAT TT=0.088 T1=0.08	SAT TT=0.088 T1=0.08	SAT TT=0.089 T1=0.08	? (TO) TT=1800.06	? (TO) TT=1800.16	? (TO) TT=1800.33	SAT TT=47.436 T1=47.42	SAT TT=56.226 T1=56.23	SAT TT=0.025 T1=0.02
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga35_33_sat_pb.cnf.cr.opb	SAT TT=0.167 T1=0.16	SAT TT=4.122 T1=4.34	SAT TT=1.055 T1=1.05	SAT TT=0.167 T1=0.16	SAT TT=4.788 T1=4.78	? (TO) TT=1800.04	? (TO) TT=1800.14	? (TO) TT=1800.33	SAT TT=60.276 T1=60.27	SAT TT=84.59 T1=84.59	SAT TT=25.397 T1=25.39
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga35_34_sat_pb.cnf.cr.opb	SAT TT=0.037 T1=0.03	SAT TT=4.23 T1=4.14	SAT TT=0.148 T1=0.14	SAT TT=0.15 T1=0.14	SAT TT=0.149 T1=0.14	? (TO) TT=1800.12	? (TO) TT=1800.21	? (TO) TT=1800.38	SAT TT=85.835 T1=85.83	SAT TT=91.021 T1=91.05	SAT TT=0.037 T1=0.03
Bench name	Best results	BoolVar 2009-04-26 (complete)	bsolo 3.1 (complete)	bsolo 3.1 cl (complete)	bsolo 3.1 pb (complete)	pbclasp 2009-04-24 (complete)	SAT4J Pseudo CP 2.1.1 (complete)	SAT4J Pseudo Resolution 2.1.1 (complete)	SCIPclp SCIP 1.1.0.7 with CLP 1.8.2 (complete)	SCIPspx SCIP 1.1.0.7 with SoPLEX 1.4.1(24.4.2009) (complete)	wbo 1.0 (complete)
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga35_35_sat_pb.cnf.cr.opb	SAT TT=0.057 T1=0.05	? (TO) TT=1800.14	SAT TT=0.187 T1=0.18	SAT TT=0.204 T1=0.2	SAT TT=0.199 T1=0.19	? (TO) TT=1800.06	SAT TT=252.658 T1=247.93	? (TO) TT=1800.41	SAT TT=116.591 T1=116.58	SAT TT=116.318 T1=116.32	SAT TT=0.057 T1=0.05
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga40_38_sat_pb.cnf.cr.opb	SAT TT=0.054 T1=0.05	SAT TT=6.957 T1=6.84	SAT TT=0.24 T1=0.23	SAT TT=0.238 T1=0.23	SAT TT=0.222 T1=0.22	? (TO) TT=1800.12	? (TO) TT=1800.18	? (TO) TT=1800.41	SAT TT=147.678 T1=147.68	SAT TT=161.067 T1=161.07	SAT TT=0.054 T1=0.05
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga40_39_sat_pb.cnf.cr.opb	SAT TT=0.498 T1=0.49	SAT TT=157.891 T1=157.86	SAT TT=0.498 T1=0.49	SAT TT=4.126 T1=4.12	SAT TT=3.624 T1=3.62	? (TO) TT=1800.08	? (TO) TT=1800.25	? (TO) TT=1800.45	SAT TT=108.591 T1=108.58	SAT TT=169.322 T1=169.34	SAT TT=1.172 T1=1.17
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga40_40_sat_pb.cnf.cr.opb	SAT TT=0.315 T1=0.31	? (MO) TT=449.54	SAT TT=0.315 T1=0.31	SAT TT=0.315 T1=0.31	SAT TT=0.327 T1=0.32	? (TO) TT=1800.07	SAT TT=59.422 T1=56.35	? (TO) TT=1800.41	SAT TT=167.5 T1=167.51	SAT TT=144.613 T1=144.62	SAT TT=0.424 T1=0.42
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga45_43_sat_pb.cnf.cr.opb	SAT TT=0.406 T1=0.4	SAT TT=12.226 T1=12.13	SAT TT=2.169 T1=2.16	SAT TT=0.406 T1=0.4	? TT=1799.62	? (TO) TT=1800.07	? (TO) TT=1800.11	? (TO) TT=1800.41	SAT TT=170.595 T1=170.58	SAT TT=304.098 T1=304.13	SAT TT=336.862 T1=336.9
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga45_44_sat_pb.cnf.cr.opb	SAT TT=0.458 T1=0.45	SAT TT=11.098 T1=10.99	SAT TT=0.61 T1=0.6	SAT TT=0.458 T1=0.45	SAT TT=1.131 T1=1.12	? (TO) TT=1800.06	? (TO) TT=1800.17	? (TO) TT=1800.47	SAT TT=200.066 T1=200.07	SAT TT=325.7 T1=325.77	SAT TT=0.619 T1=0.61
normalized-PB06/SATUNSAT-SMALLINT/ submitted-PB05/aloul/FPGA_SAT05/ normalized-fpga45_45_sat_pb.cnf.cr.opb	SAT TT=0.141 T1=0.14	? (MO) TT=120.018	SAT TT=0.736 T1=0.73	SAT TT=0.597 T1=0.59	SAT TT=13.257 T1=13.25	? (TO) TT=1800.08	? (TO) TT=1800.24	? (TO) TT=1800.4	SAT TT=274.825 T1=274.84	SAT TT=309.648 T1=309.68	SAT TT=0.141 T1=0.14

Statistics		BoolVar 2009-04-26 (complete)	bsolo 3.1 (complete)	bsolo 3.1 cl (complete)	bsolo 3.1 pb (complete)	pbclasp 2009-04-24 (complete)	SAT4J Pseudo CP 2.1.1 (complete)	SAT4J Pseudo Resolution 2.1.1 (complete)	SCIPclp SCIP 1.1.0.7 with CLP 1.8.2 (complete)	SCIPspx SCIP 1.1.0.7 with SoPLEX 1.4.1(24.4.2009) (complete)	wbo 1.0 (complete)
Number of times the solver is able to give the best known answer		29	57	38	55	21	43	9	57	57	37
Number of times the solver is the best solver from a complete solver point of view (i.e. best known answer and best TT time)		0	9	6	4	0	0	0	13	1	26