PB'07 evaluation: results by benchmark

Results by benchmark for category optimisation, small integers, linear constraints (OPT-SMALLINT-LIN), subcategory Handmade, subsubcategory Synthesis PTL/CMOS Circuits

This page displays the results of the different solvers for each benchmark for category optimisation, small integers, linear constraints (OPT-SMALLINT-LIN), subcategory Handmade, subsubcategory Synthesis PTL/CMOS Circuits

REMINDER

Keep in mind that the 'Best result' columns only provide the best result given by one of the solvers. This 'Best result' may be wrong in case of an UNSATISFIABLE or OPTIMUM FOUND answer (because there's no efficient way to check these answers).

Description of a cell contents:

Cell exampleMeaning
AnswerSolver result
f=...value of the objective function for the model reported by the solver
TT=...Total Time (TT): this is the CPU time (in seconds) used by the solver until termination. This time is only meaningful for complete solvers because incomplete solvers will always run until they time out
T1=...Time to get the best model (T1): this is the wall clock time (in seconds) ellapsed when the solver found its best model. This time is obtained from the 'o lines'. It is useful to compare both complete and incomplete solvers. It doesn't take into account the time to prove optimality of the solution.
Remember that CPU time and wall clock time are two very different notions. The CPU time represents the time during which the instructions of the solver were executed by the processor. The wall clock time represents how much time ellapsed on the clock. For a same event, the CPU time may be either smaller or greater than the wall clock time depending on the number of threads of execution and the number of processors.

Meaning of some abbreviations:

AbbreviationMeaning
f=...Value of the objective function
TOTime Out
MOMem. Out (out of memory)

Meaning of the different colors:

ColorMeaning
textthe solver cannot handle this instance
textthe solver gave no answer
textthe solver could give an answer (SAT)
textthe solver gave a definitive answer (OPTIMUM FOUND or UNSAT)
textthe solver performed better than the other ones on that instance (complete solvers point of view)
textthe solver performed better than the other ones on that instance (incomplete solvers point of view)
textthe solver was ended by a signal or other problem
textthe solver gave an incomplete answer
textthe solver gave a wrong answer

For better readability, you may choose to hide some solvers:
absconPseudo 102
bsolo 3.0.16
bsolo 3.0.17
glpPB 0.2
minisat+ 1.14
oree 0.1.2 alpha
PB-clasp 2007-03-23
PB-clasp 2007-04-10
PBS4 2007-03-23
PBS4_v2 2007-03-23
Pueblo 1.4
sat4jPseudoCP 2007-03-23
sat4jPseudoCPClause 2007-03-23
SAT4JPseudoResolution 2007-03-23
wildcat-rnp 2007-03-21
wildcat-skc 2007-03-21

Bench nameBest results
on this
instance
absconPseudo
102
bsolo
3.0.16
bsolo
3.0.17
glpPB
0.2
minisat+
1.14
oree
0.1.2 alpha
PB-clasp
2007-03-23
PB-clasp
2007-04-10
PBS4
2007-03-23
PBS4_v2
2007-03-23
Pueblo
1.4
sat4jPseudoCP
2007-03-23
sat4jPseudoCPClause
2007-03-23
SAT4JPseudoResolution
2007-03-23
wildcat-rnp
2007-03-21
wildcat-skc
2007-03-21
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-9symml.opb
OPT
f=4517
TT=4.777
T1=4.69
SAT (TO)
f=6087
TT=1800.08
T1=265.04
OPT
f=4517
TT=440.407
T1=438.73
OPT
f=4517
TT=166.433
T1=165.42
OPT
f=4517
TT=4.777
T1=4.69
SAT (TO)
f=5231
TT=1800.05
T1=1331.03
SAT (TO)
f=5505
TT=1800.17
T1=798
SAT (MO)
f=11935
TT=21.26
T1=0.16
SAT (TO)
f=7054
TT=1801.98
T1=1.58
No Cert.

TT=1800.11

SAT (TO)
f=5155
TT=1800.07
T1=374.3
SAT
f=5274
TT=1782.73
T1=33.57
SAT (TO)
f=5962
TT=1800.27
T1=7.63
SAT (TO)
f=5962
TT=1800.27
T1=7.58
SAT (TO)
f=5987
TT=1800.32
T1=2.06
SAT (TO)
f=6039
TT=1800.07
T1=1534.82
SAT (TO)
f=4966
TT=1800.01
T1=1624.34
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-C432.opb
OPT
f=4822
TT=121.089
T1=86.06
SAT (TO)
f=7120
TT=1800.12
T1=0.48
SAT
f=4822
TT=1800.01
T1=1760.64
OPT
f=4822
TT=121.089
T1=86.06
OPT
f=4822
TT=132.059
T1=131.96
SAT (TO)
f=6251
TT=1800.08
T1=1177.38
SAT (TO)
f=5507
TT=1800.11
T1=0.09
SAT (MO)
f=13787
TT=24.95
T1=0.19
SAT (TO)
f=6921
TT=1802.06
T1=0.51
No Cert.

TT=1800.06

SAT (TO)
f=6116
TT=1800.11
T1=79.76
SAT
f=5610
TT=1782.73
T1=0
SAT (TO)
f=6933
TT=1800.23
T1=19.61
SAT (TO)
f=6949
TT=1800.21
T1=1.31
SAT (TO)
f=6931
TT=1800.46
T1=4.59
SAT (TO)
f=7173
TT=1800.05
T1=1423.91
SAT (TO)
f=5742
TT=1800.06
T1=1162.69
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-c8.opb
OPT
f=1194
TT=0.113
T1=0.06
SAT (TO)
f=1570
TT=1800.03
T1=0.5
OPT
f=1194
TT=0.244
T1=0.09
OPT
f=1194
TT=0.113
T1=0.06
OPT
f=1194
TT=0.319
T1=0.29
SAT (TO)
f=1356
TT=1800.07
T1=404.09
SAT (TO)
f=1325
TT=1800.25
T1=0.01
SAT (MO)
f=4439
TT=29.9
T1=0.05
SAT (TO)
f=1569
TT=1802.06
T1=910.45
No Cert.

TT=1800.05

SAT (TO)
f=1309
TT=1800.03
T1=1442.81
SAT
f=1309
TT=1782.73
T1=991.2
SAT (TO)
f=1556
TT=1800.22
T1=88.51
SAT (TO)
f=1560
TT=1800.3
T1=5.07
SAT (TO)
f=1569
TT=1800.3
T1=3.37
SAT (TO)
f=1441
TT=1800.05
T1=913.66
SAT (TO)
f=1218
TT=1800.04
T1=585.84
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-cc.opb
OPT
f=1567
TT=0.024
T1=0
SAT (TO)
f=1646
TT=1800.07
T1=218.05
OPT
f=1567
TT=0.055
T1=0
OPT
f=1567
TT=0.048
T1=0.01
OPT
f=1567
TT=0.024
T1=0
SAT (TO)
f=1633
TT=1800.06
T1=44.28
SAT (TO)
f=1643
TT=1800.35
T1=1.09
SAT (MO)
f=3274
TT=29.29
T1=0
SAT (TO)
f=1752
TT=1802.13
T1=1.01
No Cert.

TT=1800.1

SAT (TO)
f=1584
TT=1800.08
T1=119.56
SAT
f=1586
TT=1782.74
T1=60.95
SAT (TO)
f=1576
TT=1800.14
T1=827.21
SAT (TO)
f=1648
TT=1800.24
T1=1380.38
SAT (TO)
f=1625
TT=1800.28
T1=1257.28
SAT (TO)
f=1619
TT=1800.07
T1=1305.83
SAT (TO)
f=1575
TT=1800.06
T1=183.65
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-cm42a.opb
OPT
f=694
TT=0.036
T1=0
SAT (TO)
f=836
TT=1800.05
T1=1517.11
OPT
f=694
TT=0.053
T1=0
OPT
f=694
TT=0.036
T1=0
OPT
f=694
TT=0.057
T1=0.05
OPT
f=694
TT=550.954
T1=243.82
SAT (TO)
f=698
TT=1800.21
T1=152.04
SAT (MO)
f=2344
TT=28.23
T1=0
SAT (TO)
f=694
TT=1802.08
T1=616.89
No Cert.

TT=1800.08

SAT (TO)
f=694
TT=1800.05
T1=1306.05
SAT
f=694
TT=1782.73
T1=559
SAT (TO)
f=785
TT=1800.18
T1=26.35
SAT (TO)
f=760
TT=1800.15
T1=1791.48
SAT (TO)
f=794
TT=1800.17
T1=1700.37
SAT (TO)
f=813
TT=1800.1
T1=43.28
SAT (TO)
f=696
TT=1800.04
T1=1056.83
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-cmb.opb
OPT
f=1053
TT=0.097
T1=0
SAT (TO)
f=1501
TT=1800.08
T1=0.48
OPT
f=1053
TT=0.091
T1=0.01
OPT
f=1053
TT=0.103
T1=0.01
OPT
f=1053
TT=0.097
T1=0
SAT (TO)
f=1324
TT=1800.08
T1=341.86
SAT (TO)
f=1053
TT=1800.26
T1=1570.67
SAT (MO)
f=5496
TT=27.29
T1=0
SAT (TO)
f=1363
TT=1802.09
T1=0.16
No Cert.

TT=1800.12

SAT (TO)
f=1101
TT=1800.06
T1=1121.77
SAT
f=1057
TT=1782.73
T1=0
SAT (TO)
f=1524
TT=1800.21
T1=6.13
SAT (TO)
f=1524
TT=1800.18
T1=714.12
SAT (TO)
f=1552
TT=1800.29
T1=525.63
SAT (TO)
f=1369
TT=1800.07
T1=1006.08
SAT (TO)
f=1053
TT=1800.04
T1=1481.3
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-mux.opb
OPT
f=872
TT=0.029
T1=0
SAT (TO)
f=1296
TT=1800.05
T1=0.68
OPT
f=872
TT=0.027
T1=0
OPT
f=872
TT=0.029
T1=0
OPT
f=872
TT=0.032
T1=0
SAT (TO)
f=1196
TT=1800.12
T1=25.78
SAT (TO)
f=882
TT=1800.25
T1=0
SAT (MO)
f=3076
TT=28.61
T1=0.07
SAT (TO)
f=1370
TT=1802.1
T1=1424.9
No Cert.

TT=1800.1

SAT (TO)
f=1017
TT=1800.03
T1=1750.06
SAT
f=882
TT=1782.73
T1=0
SAT (TO)
f=1391
TT=1800.27
T1=19.61
SAT (TO)
f=1472
TT=1800.24
T1=32.76
SAT (TO)
f=1605
TT=1800.26
T1=0.82
SAT (TO)
f=1390
TT=1800.04
T1=1781.72
SAT (TO)
f=882
TT=1800.05
T1=1008.76
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/synthesis-ptl-cmos-circuits/
normalized-my_adder.opb
OPT
f=4561
TT=2.264
T1=1.49
SAT (TO)
f=6071
TT=1800.14
T1=0.49
OPT
f=4561
TT=3.683
T1=2.19
OPT
f=4561
TT=2.264
T1=1.49
? (TO)

TT=1800.1

SAT (TO)
f=5534
TT=1800.05
T1=1296.1
SAT (TO)
f=5790
TT=1800.2
T1=0
SAT (MO)
f=10213
TT=28.85
T1=0.13
SAT (TO)
f=6953
TT=1802.02
T1=0.01
No Cert.

TT=1800.08

SAT (TO)
f=5792
TT=1800.12
T1=1324.79
SAT
f=4981
TT=1782.73
T1=0
SAT (TO)
f=5679
TT=1800.16
T1=47.47
SAT (TO)
f=6037
TT=1800.24
T1=12.02
SAT (TO)
f=6092
TT=1800.18
T1=0.77
SAT (TO)
f=6418
TT=1800.08
T1=1655.9
SAT (TO)
f=5097
TT=1800.1
T1=1639.11

Some statistics...

absconPseudo
102
bsolo
3.0.16
bsolo
3.0.17
glpPB
0.2
minisat+
1.14
oree
0.1.2 alpha
PB-clasp
2007-03-23
PB-clasp
2007-04-10
PBS4
2007-03-23
PBS4_v2
2007-03-23
Pueblo
1.4
sat4jPseudoCP
2007-03-23
sat4jPseudoCPClause
2007-03-23
SAT4JPseudoResolution
2007-03-23
wildcat-rnp
2007-03-21
wildcat-skc
2007-03-21
Number of times the solver is able to give the best known answer0087100000000000
Number of times the solver is able to give the best known answer from an incomplete solver point of view (i.e. without considering optimality proof)0087110101100001
Number of times the solver is the best solver from a complete solver point of view (i.e. best known answer and best TT time)0053000000000000
Number of times the solver is the best solver from an incomplete solver point of view (i.e. best known answer and best T1 time)0054000000000000