PB'06 evaluation: results by benchmark

Results by benchmark for category optimisation, small integers (OPT-SMALLINT), subcategory Handmade, subsubcategory Synthesis PTL/CMOS Circuits

This page displays the results of the different solvers for each benchmark for category optimisation, small integers (OPT-SMALLINT), subcategory Handmade, subsubcategory Synthesis PTL/CMOS Circuits

REMINDER

Keep in mind that the 'Best result' columns only provide the best result given by one of the solvers. This 'Best result' may be wrong in case of an UNSATISFIABLE or OPTIMUM FOUND answer (because there's no efficient way to check these answers).

Description of a cell contents:

Cell exampleMeaning
AnswerSolver result
f=...value of the objective function for the model reported by the solver
TT=...Total Time (TT): this is the CPU time (in seconds) used by the solver until termination. This time is only meaningful for complete solvers because incomplete solvers will always run until they time out
T1=...Time to get the best model (T1): this is the wall clock time (in seconds) ellapsed when the solver found its best model. This time is obtained from the 'o lines'. It is useful to compare both complete and incomplete solvers. It doesn't take into account the time to prove optimality of the solution.
Remember that CPU time and wall clock time are two very different notions. The CPU time represents the time during which the instructions of the solver were executed by the processor. The wall clock time represents how much time ellapsed on the clock. For a same event, the CPU time may be either smaller or greater than the wall clock time depending on the number of threads of execution and the number of processors.

Meaning of some abbreviations:

AbbreviationMeaning
f=...Value of the objective function
TOTime Out
MOMem. Out (out of memory)

Meaning of the different colors:

ColorMeaning
textthe solver cannot handle this instance
textthe solver gave no answer
textthe solver could give an answer (SAT)
textthe solver gave a definitive answer (OPTIMUM FOUND or UNSAT)
textthe solver performed better than the other ones on that instance (complete solvers point of view)
textthe solver performed better than the other ones on that instance (incomplete solvers point of view)
textthe solver was ended by a signal or other problem
textthe solver gave an incomplete answer
textthe solver gave a wrong answer

For better readability, you may choose to hide some solvers:
absconPseudo 1
bsolo 2006/05
glpPB 0.2
minisat+ 1.14
PBS 4.1L
PB-smodels 1.28
PB-smodels 1.31
Pueblo 1.3
Pueblo 1.4
SAT4JPSEUDO 2006.2
SAT4JPSEUDO 2006.2 Heuristics
wildcat-rnp 0.8.0
wildcat-skc 0.8.0

Bench nameBest results
on this
instance
absconPseudo
1
bsolo
2006/05
glpPB
0.2
minisat+
1.14
PBS
4.1L
PB-smodels
1.28
PB-smodels
1.31
Pueblo
1.3
Pueblo
1.4
SAT4JPSEUDO
2006.2
SAT4JPSEUDO
2006.2 Heuristics
wildcat-rnp
0.8.0
wildcat-skc
0.8.0
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-9symml.opb
OPT
f=4517
TT=4.759
T1=4.76
SAT (TO)
f=6087
TT=1800.48
T1=214.68
OPT
f=4517
TT=190.256
T1=137.3
OPT
f=4517
TT=4.759
T1=4.76
SAT (TO)
f=5231
TT=1800.71
T1=1329.34
? (TO)

TT=1800.65

SAT (TO)
f=5348
TT=1800.85
T1=396.47
SAT (TO)
f=5484
TT=1800.77
T1=2.74
SAT
f=5274
TT=1782.74
T1=30.72
SAT
f=5274
TT=1782.74
T1=33.66
SAT (TO)
f=5439
TT=1800.59
T1=512.65
SAT (TO)
f=5690
TT=1801.12
T1=1170.43
SAT (TO)
f=6056
TT=1800.51
T1=1511.8
SAT (TO)
f=4894
TT=1800.66
T1=1766.19
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-b1.opb
OPT
f=128
TT=0.002
T1=0
OPT
f=128
TT=0.908
T1=0.95
OPT
f=128
TT=0.011
T1=0.19
OPT
f=128
TT=0.006
T1=0
OPT
f=128
TT=0.007
T1=0
OPT
f=128
TT=0.002
T1=0
OPT
f=128
TT=0.036
T1=0.03
OPT
f=128
TT=0.042
T1=0.03
OPT
f=128
TT=0.004
T1=0
OPT
f=128
TT=0.005
T1=0
OPT
f=128
TT=0.298
T1=0.25
OPT
f=128
TT=0.394
T1=0.3
SAT (TO)
f=128
TT=1800.55
T1=9.41
SAT (TO)
f=128
TT=1800.62
T1=3.87
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-C17.opb
OPT
f=260
TT=0.001
T1=0
OPT
f=260
TT=0.995
T1=0.68
OPT
f=260
TT=0.013
T1=0.02
OPT
f=260
TT=0.006
T1=0
OPT
f=260
TT=0.005
T1=0
OPT
f=260
TT=0.001
T1=0
OPT
f=260
TT=0.037
T1=0.02
OPT
f=260
TT=0.035
T1=0.02
OPT
f=260
TT=0.002
T1=0
OPT
f=260
TT=0.002
T1=0
OPT
f=260
TT=0.28
T1=0.25
OPT
f=260
TT=0.347
T1=0.25
SAT (TO)
f=260
TT=1800.62
T1=0
SAT (TO)
f=260
TT=1800.69
T1=3.95
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-C432.opb
OPT
f=4822
TT=132.429
T1=132.46
SAT (TO)
f=7120
TT=1800.6
T1=1.2
OPT
f=4822
TT=586.508
T1=322.24
OPT
f=4822
TT=132.429
T1=132.46
SAT (TO)
f=6251
TT=1800.69
T1=1175.8
? (TO)

TT=1800.52

SAT (TO)
f=6670
TT=1800.89
T1=48.92
SAT (TO)
f=6053
TT=1800.8
T1=1722.37
SAT
f=5610
TT=1782.74
T1=0.07
SAT
f=5610
TT=1782.73
T1=0.07
SAT (TO)
f=6281
TT=1801.08
T1=58.74
SAT (TO)
f=6933
TT=1800.18
T1=2.08
SAT (TO)
f=7177
TT=1800.55
T1=1102.09
SAT (TO)
f=5668
TT=1800.66
T1=1679.28
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-c8.opb
OPT
f=1194
TT=0.323
T1=0.32
SAT (TO)
f=1570
TT=1800.34
T1=0.85
OPT
f=1194
TT=0.408
T1=0.4
OPT
f=1194
TT=0.323
T1=0.32
SAT (TO)
f=1356
TT=1800.51
T1=388.31
? (TO)

TT=1800.67

SAT (TO)
f=1259
TT=1800.54
T1=5.66
SAT (TO)
f=1250
TT=1800.76
T1=531.68
SAT
f=1309
TT=1782.74
T1=752.8
SAT
f=1309
TT=1782.73
T1=997.24
SAT (TO)
f=1396
TT=1800.3
T1=161.33
SAT (TO)
f=1377
TT=1800.79
T1=455.54
SAT (TO)
f=1437
TT=1800.71
T1=1691.09
SAT (TO)
f=1212
TT=1800.16
T1=371.21
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-cc.opb
OPT
f=1567
TT=0.02
T1=0.02
SAT (TO)
f=1636
TT=1800.32
T1=1529.52
OPT
f=1567
TT=0.02
T1=0.03
OPT
f=1567
TT=0.023
T1=0.02
SAT (TO)
f=1633
TT=1800.58
T1=44.01
? (TO)

TT=1800.7

SAT (TO)
f=1677
TT=1800.63
T1=0.08
SAT (TO)
f=1567
TT=1800.81
T1=0.05
SAT
f=1584
TT=1782.73
T1=1526.79
SAT
f=1586
TT=1782.74
T1=61.71
SAT (TO)
f=1567
TT=1801.1
T1=477.18
OPT
f=1567
TT=489.166
T1=160.74
SAT (TO)
f=1644
TT=1800.47
T1=174.19
SAT (TO)
f=1567
TT=1800.5
T1=339.76
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-cm42a.opb
OPT
f=694
TT=0.055
T1=0.05
SAT (TO)
f=819
TT=1800.29
T1=1363.85
OPT
f=694
TT=0.083
T1=0.07
OPT
f=694
TT=0.055
T1=0.05
OPT
f=694
TT=551.065
T1=244.08
? (TO)

TT=1800.53

SAT (TO)
f=694
TT=1800.61
T1=35.92
SAT (TO)
f=694
TT=1800.76
T1=0.1
OPT
f=694
TT=1585.29
T1=422.47
SAT
f=694
TT=1782.73
T1=561.84
SAT (TO)
f=726
TT=1800.16
T1=170.61
SAT (TO)
f=696
TT=1800.78
T1=407.79
SAT (TO)
f=806
TT=1800.68
T1=411.88
SAT (TO)
f=696
TT=1800.69
T1=53.16
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-cmb.opb
OPT
f=1053
TT=0.095
T1=0.09
SAT (TO)
f=1501
TT=1800.29
T1=0.89
OPT
f=1053
TT=0.451
T1=0.15
OPT
f=1053
TT=0.095
T1=0.09
SAT (TO)
f=1324
TT=1800.58
T1=342.75
? (TO)

TT=1800.8

SAT (TO)
f=1079
TT=1800.64
T1=0.16
SAT (TO)
f=1106
TT=1800.71
T1=0.13
SAT
f=1057
TT=1782.74
T1=0.02
SAT
f=1057
TT=1782.74
T1=0.02
SAT (TO)
f=1333
TT=1801.04
T1=64.97
SAT (TO)
f=1468
TT=1800.25
T1=4.51
SAT (TO)
f=1379
TT=1800.78
T1=113.85
SAT (TO)
f=1053
TT=1800.65
T1=671.03
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/
synthesis-ptl-cmos-circuits/normalized-mux.opb
OPT
f=872
TT=0.032
T1=0.03
SAT (TO)
f=1296
TT=1800.37
T1=1.1
OPT
f=872
TT=0.055
T1=0.11
OPT
f=872
TT=0.032
T1=0.03
SAT (TO)
f=1196
TT=1800.71
T1=25.89
? (TO)

TT=1800.72

SAT (TO)
f=897
TT=1800.76
T1=1091.8
SAT (TO)
f=1022
TT=1800.66
T1=983.44
SAT
f=882
TT=1782.73
T1=0.01
SAT
f=882
TT=1782.73
T1=0.01
SAT (TO)
f=1146
TT=1800.36
T1=232.95
SAT (TO)
f=1225
TT=1801.06
T1=2.45
SAT (TO)
f=1405
TT=1800.71
T1=530.63
SAT (TO)
f=882
TT=1800.63
T1=417.94
normalized-PB06/OPT-SMALLINT/
submitted-PB05/manquinho/synthesis-ptl-cmos-circuits/
normalized-my_adder.opb
OPT
f=4561
TT=12.602
T1=10.81
SAT (TO)
f=6071
TT=1800.62
T1=1.01
OPT
f=4561
TT=12.602
T1=10.81
? (TO)

TT=1800.51

SAT (TO)
f=5534
TT=1801.05
T1=1253.11
? (TO)

TT=1800.71

SAT (TO)
f=5808
TT=1800.68
T1=1404.64
SAT (TO)
f=5652
TT=1800.84
T1=33.91
SAT
f=4981
TT=1782.73
T1=0.03
SAT
f=4981
TT=1782.73
T1=0.03
SAT (TO)
f=5246
TT=1800.78
T1=1170.31
SAT (TO)
f=5003
TT=1800.93
T1=373.58
SAT (TO)
f=6401
TT=1800.68
T1=1169.1
SAT (TO)
f=5103
TT=1800.58
T1=1552.5

Some statistics...

absconPseudo
1
bsolo
2006/05
glpPB
0.2
minisat+
1.14
PBS
4.1L
PB-smodels
1.28
PB-smodels
1.31
Pueblo
1.3
Pueblo
1.4
SAT4JPSEUDO
2006.2
SAT4JPSEUDO
2006.2 Heuristics
wildcat-rnp
0.8.0
wildcat-skc
0.8.0
Number of times the solver is able to give the best known answer21093222322300
Number of times the solver is able to give the best known answer from an incomplete solver point of view (i.e. without considering optimality proof)21093234333324
Number of times the solver is the best solver from a complete solver point of view (i.e. best known answer and best TT time)0260200000000
Number of times the solver is the best solver from an incomplete solver point of view (i.e. best known answer and best T1 time)0192200220010